1. Field of Invention
This invention relates to semiconductor device formation, and particularly to raised source-drain MOSFET device formation.
2. Related Art
One trend of the semiconductor industry is to make semiconductor devices as small as possible. Often, however, process technology or the methods used in forming many devices impose limitations on how small a device can be made.
A typical semiconductor device and a primary building block in the semiconductor industry is the metal oxide semiconductor field effect transistor (MOSFET). A cross-section of a MOSFET is shown in FIG. 1. A MOSFET is typically composed of a gate 120 and an insulating gate oxide layer 115 both formed over a silicon substrate 110. Gate 120 is usually composed of polysilicon. Within substrate 110 are formed deep source-drain regions 150 (sometimes referred to as heavily doped source and drain regions) and source-drain extension regions 130 (sometimes referred to as lightly doped source and drain regions). Generally, doped regions are regions containing a higher concentration of p-type or n-type dopants than the substrate. Source-drain extension regions 130 generally have a lower concentration of dopants compared to deep source-drain regions 150, although some technologies allow the regions to be doped at equivalent levels. Further source-drain extension regions 130 have a thickness t.sub.1 which is smaller than thickness t.sub.2 of deep source-drain regions 150. Shallow source-drain extension regions 130 are important for reducing hot carrier injection (HCI), which often occurs in scaled down (e.g., sub-micron) devices, and for maintaining other device characteristics such as threshold voltage rolloff, punchthrough, and other short channel characteristics. Thicker deep source-drain regions are generally important for lowering device resistivity, for maximizing drive current and for forming contacts.
In reducing the size of MOSFET devices, much of the focus has been on reducing the length L of the gate 120. As the gate length L is reduced, however, the device size must also be reduced in the vertical direction--that is, the source-drain extension region thickness t.sub.1 must be reduced. Formation of shallow source-drain extension regions, however, requires precise control of dopant distribution on a fine scale. Unfortunately, while technology will allow other portions of MOSFET devices to be scaled smaller, e.g., gates scaled to sub-micron lengths, limitations in forming finely scaled source-drain extension regions have prevented semiconductor devices from reaching their smallest dimensions. These limitations often arise as a result of heat steps, including anneal processes which are required to repair and activate doped regions, but which also cause dopant diffusion.
One proposed structure which allows for smaller device scaling while avoiding small scale source-drain extension formation problems is a raised source-drain MOSFET. One type of raised source-drain MOSFET is the hot-carrier suppressed (HCS) MOSFET, a cross-section of which is shown in FIG. 2. An HCS MOSFET includes substrate 210, gate oxide 215 of approximately 70 .ANG. in thickness, gate 220, and sidewall oxides 270 of approximately 200 .ANG. in width. The HCS MOSFET has source and drain regions 240 in substrate 210.
Rather than using source-drain extension regions, an HCS MOSFET has elevated N.sup.- epitaxial layers 250 which perform the same functions as source-drain extension regions in conventional MOSFETs but avoid the deepening diffusion problem in their formation. That is, layers 250 reduce, or suppress, hot-carrier injection. N.sup.- layer 250 is approximately 1000 .ANG. in thickness and has a doping concentration on the order of 10.sup.16 cm.sup.-3.
In order to provide lower sheet and contact resistance, a second N.sup.+ epitaxial layer 260 is utilized. N.sup.+ layer 260 is approximately 1000 .ANG. in thickness with a doping concentration on the order of 10.sup.20 cm.sup.-3.
Because many of the functions of the deep source-drain regions of conventional MOSFETs are fulfilled by the second epitaxial layer 260, HCS MOSFET source and drain regions 240 can remain shallow, which is desirable in forming smaller devices, at approximately 600 .ANG. with a doping concentration on the order of 10.sup.18. More detailed information regarding the general structure and performance of HCS MOSFET devices can be found in Shin et al., "MOSFET Drain Engineering Analysis for Deep-Submicrometer Dimensions: A New Structural Approach," IEEE Transactions on Electron Devices, Vol. 39, No. 8 (August 1992).
While raised source-drain MOSFETs have comparable performance characteristics to those of conventional MOSFETs while at the same time permitting the formation of smaller devices when compared with conventional MOSFETS, use of raised source-drain MOSFETs has not become widespread. The devices are difficult to manufacture for at least three reasons. First, as shown in the HCS device of FIG. 2, the raised epitaxial layers 250 and 260 must be selectively grown, which is a difficult task involving high vacuum and chemical vapor deposition processes. Such processes further require expensive equipment, are difficult to control, critically rely on surface preparation, and are easily ruined by a small amount of contamination.
Second, source and drain regions 240 are doped using conventional methods, e.g., by ion implantation, prior to forming the epitaxial layers. For the same reasons that source-drain extension region depth in a conventional MOSFET is difficult to control, so too is it difficult to maintain shallow source and drain regions 240, which are desirable in forming small scale raised source-drain MOSFETs: the heat cycles in the epitaxial (epi) layer formation cause the dopants to diffuse.
Finally, the quality of the sidewall oxides 270 in these raised source-drain MOSFETs is generally lacking. Sidewalls of sufficient uniform thickness are necessary to control capacitance between the gate and the raised source-drain regions 250 and 260. Such sidewall oxides however, are generally grown or deposited on the gate prior to forming epi layers 250 and 260, and the ability to form sidewalls of adequate uniform thickness to sufficiently control capacitance is extremely difficult, particularly when subjected to the cycles required for epitaxy.
Therefore, it is desirable to develop a process that will allow for easier manufacturability of raised source-drain MOSFETs, and thus allow for semiconductor device formation of reduced size.